1. Technical Field
Example embodiments relate to a memory interface circuit and a memory system, and more particularly to the memory interface circuit capable of decreasing the number of delay locked loops, and a memory system including the memory interface circuit.
2. Description of the Related Art
Typically, a master delay locked loop and a plurality of slave delay locked loops may be utilized to generate signals for writing or reading data in high-speed semiconductor memory device, e.g., double data rate synchronous dynamic random access memory (DDR SDRAM). For example, a signal delayed by a phase of 270 degrees with respect to a clock signal may be utilized to write data to a memory block and a signal delayed by a phase of 90 degrees with respect to a data strobe signal may be utilized to read data from the memory block. The master delay locked loop and the slave delay locked loops may be utilized in a double data rate memory to delay the signals. The signals may be delayed by respective slave delay locked loops because the delayed phase of the delayed clock signal for writing data may be different from the delayed phase of the delayed data strobe signal for reading data. Typically, the double data rate memory requires two slave delay locked loops per 8 bits. As the number of the delay locked loops in the memory interface circuit may be increased, a size of a semiconductor chip may be increased and power consumption may also be increased.